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Anti-aliasing RC filter calculator

Check an RC input filter against the ADC: corner frequency, attenuation at half the sample rate, settling to ½ LSB and delay.

Filter

Stages

Settling to ½ LSB takes 901.1 µs, longer than one sample period (100 µs). This matters when the ADC is multiplexed between channels or the input steps; a continuously filtered signal only lags.

ADC

Result

−3 dB frequency
1.592 kHz1 / (2π R C)
Time constant
100 µsR × C = 1 kΩ × 100 nF
Attenuation at Nyquist
-10.36 dBat 5 kHz, gain 0.3033
Needed for ½ LSB
-78.27 dB67.9 dB short: content near half the sample rate aliases above ½ LSB
Settling to ½ LSB
901.1 µs9.01 τ; one sample period is 100 µs
Delay
100 µsgroup delay at low frequencies, n τ
Amplitude loss at 100 Hz
0.197 %phase -3.6°
Attenuation at 50 Hz
-0.004284 dBgain 0.9995

Schematic

Measuring inputR1 kΩ100 nFC× 1−3 dB: 1.592 kHzADC12 bitfs = 10 kHz
Drawn from the inputs above; not to scale.
Formulas and standards
fc = 1 / (2π R C)   |H(f)| = (1 + (f / fc)²)−n/2
Aneeded = 20 log₁₀ 2−(N+1) dB   tsettle ≈ (N + 1) ln 2 · τ (n = 1)

Each stage has the corner frequency fc = 1 / (2π R C) and the gain 1 / √(1 + (f/fc)²); n stages separated by buffers multiply. A full-scale signal at half the sample rate folds back into the band, so for it to stay below ½ LSB the filter must attenuate it by 20 log(2^−(N+1)) dB, about 6 dB per bit. A single RC stage rarely achieves that; it is usually combined with oversampling and a digital filter.

After a step the output of n identical stages approaches the final value as 1 − e^(−t/τ) Σ (t/τ)^k / k!; settling to ½ LSB takes about (N+1) ln 2 time constants for one stage. Unbuffered RC stages load each other and give a lower corner than this calculation; the ADC's sampling capacitor and source impedance requirement also matter, so check the ADC datasheet.

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How the anti-aliasing filter calculator works

An ADC samples its input at discrete moments. Anything in the signal above half the sample rate, the Nyquist frequency, is not lost but folds back into the measured band as a false low-frequency component. A filter ahead of the ADC must remove it before it is sampled. The simplest is a resistor and a capacitor, often in front of the ADC input or a sensor’s terminals.

The calculator takes R and C, or R and the corner frequency, and shows the −3 dB frequency, the attenuation at the Nyquist frequency against what ½ LSB requires, the time to settle after a step, and the delay. It handles up to four identical stages separated by buffers.

How much attenuation is enough

For a full-scale signal at the Nyquist frequency to stay below ½ LSB, the filter must attenuate it by 20 log(2^−(N+1)): 78 dB for 12 bits, 102 dB for 16 bits. A single RC stage falls by 20 dB per decade above its corner, so with a 1.6 kHz corner and 10 kHz sampling it reaches only 10 dB at 5 kHz. The calculator states the shortfall.

In practice, real interference at the Nyquist frequency is rarely full scale, and most designs combine a simple RC filter with oversampling and a digital filter after the ADC. The figure shows how much of the work the analogue filter does.

Settling time

After a step at the input, the filter output approaches the new value exponentially. To be within ½ LSB a single stage needs (N + 1) ln 2 time constants: 9 τ for 12 bits, 11.8 τ for 16 bits. This matters when the ADC is multiplexed between channels, when the input steps, or when the source is switched on just before a measurement. A continuously sampled, filtered signal simply lags by the delay.

Signal loss and phase

The filter also attenuates the signal you want. At a tenth of the corner frequency the loss is 0.5 %; at the corner it is 29 %. Enter the signal frequency to see the amplitude loss and the phase shift, and an interference frequency, such as 50 or 60 Hz mains, to see how much of it remains.

What the calculation leaves out

Stages connected directly without buffers load each other, which lowers the corner and changes the response. The ADC’s sampling capacitor draws a charge at each conversion, and the filter capacitor must be large enough to supply it without a step; the ADC datasheet states the maximum source impedance. The ADC resolution calculator shows how many codes the sensor span uses.

Frequently asked questions

Why not choose a very low corner frequency?

A low corner removes more interference but also slows the response, delays the signal and reduces the amplitude of fast changes. Choose the corner from the fastest change you need to see, then raise the sample rate until the attenuation at Nyquist is enough.

Are two RC stages better than one?

Two stages fall at 40 dB per decade instead of 20, so they attenuate far more at Nyquist. Their −3 dB frequency is 0.64 times the corner of each stage, and they settle more slowly.

Do sigma-delta ADCs need this filter?

Much less. A sigma-delta converter samples far above the output data rate and filters digitally, so a simple RC with a corner well above the band is usually enough. Check the datasheet’s recommended input filter.

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